AI Now Designs Chips: Nvidia and Cadence Open a New Race in EDA

The next contest in chip design may turn less on building smarter AI models than on how accurately AI can run real design tools. Cadence's Maestro, built with Nvidia, is an early test.

Who draws the blueprint for a chip?

Building AI chips takes more than Nvidia's GPUs. It also takes software that designs and verifies billions of transistors so they work as intended. That software is electronic design automation, or EDA.

Cadence (CDNS) and Synopsys (SNPS) are the leading names in the field. Much as an architect checks a building's structure and safety, a chip engineer uses EDA to build circuits and check power consumption, speed, chip area and the odds of errors. A mistake missed before manufacturing can mean costly redesigns and launch delays.

Maestro is AI that operates design tools, not a chatbot

Cadence unveiled Maestro on Oct. 26. It is a portfolio of AI models specialized for semiconductor and system design. AI agents break a design goal into tasks, call EDA tools, verify the results and then decide the next task. Human review and verification have not gone away.

Cadence is working with Nvidia, using its open-weight Nemotron models and integrating agent security technology based on OpenShell. Customers can run the models in the cloud or inside their own data centers, and can train them further on proprietary design data. That is a meaningful option for customers reluctant to let core design information leave the building.

In early design-task evaluations, Cadence cited up to 30% better result quality than general-purpose foundation models and up to 5x token efficiency. Token efficiency here refers to how efficiently the AI uses the text units it processes. It does not mean design time fell by a factor of five. The first models are expected to reach some customers early in the fourth quarter of 2026.

Will general-purpose AI erode the EDA moat?

It could go either way. If general-purpose AI makes writing design code and repetitive work easier, some of the value of existing tools could shrink. On the other hand, the hardest part of chip design is not producing a plausible answer. It is verifying that the answer holds under real manufacturing conditions.

Cadence is tying its AI models to existing EDA tools, verification engines and customer workflows. If that verification layer stays important, the spread of AI could strengthen EDA vendors' competitive position. But if open models and new automation tools improve quickly, they could also pressure incumbents' pricing power.

The competitive picture is splitting too. According to Reuters, Synopsys has begun developing GPT-Synopsys with OpenAI, while Cadence stresses an approach that lets customers choose among several open and commercial models. What is confirmed so far is two different product strategies, not a final winner.

What the earnings show: opportunity and strain

Cadence's third-quarter 2026 revenue, reported the same day, was $1.633 billion, up about 22% from $1.339 billion a year earlier. Non-GAAP diluted EPS was $2.11. Backlog at quarter-end was $8.2 billion, of which $4.2 billion in remaining performance obligations is expected to be recognized as revenue within the next 12 months. The full backlog does not turn into revenue or cash right away.

The company said active customer collaborations tied to AI Super Agents exceeded 100. Its 2026 revenue outlook is $6.387 billion to $6.417 billion, implying growth of about 21% at the midpoint. But GAAP operating margin fell to 26.2% from 31.8% in the year-earlier third quarter, and non-GAAP operating margin fell to 44.1% from 47.6%. Revenue growth and margin improvement are not the same thing.

Who actually stands to profit?

If chip design time and iterative verification costs fall in a real way, cloud companies that build their own chips, fabless chipmakers and developers of custom AI chips could benefit. More design attempts per project may also lower the barrier to developing new chips somewhat.

For Cadence, the opportunities are wider tool usage among existing customers and sales of AI add-ons. For Nvidia, a broader Nemotron ecosystem and the compute demand from AI design workloads could be positives. But the size of any direct new revenue for Nvidia, and the cost savings at individual companies, have not yet been confirmed.

Cadence's Maestro, built with Nvidia's Nemotron, shows that accuracy inside real design tools, not just model quality, is where the EDA race is heading.

Insight Times Editorial Desk

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