What Happens When You Link a Million Chips Slower Than Nvidia's
Huawei's answer to Nvidia is not a faster chip. It is tying together up to a million processors so they act as one machine, a bet that the real unit of competition in AI chips is shifting from the chip to the system.
If one chip is slow, build a bigger system
Huawei unveiled its next-generation Ascend roadmap on September 17 at HUAWEI CONNECT 2026 in Shanghai. The company moved up the launch of Ascend 960DT by three quarters to the first quarter of 2027, and Ascend 960PR by one quarter to the third quarter of 2027. Reuters reported that demand for Huawei's AI computing hardware inside China has already outstripped current production capacity.
But the number that matters most from this announcement is not 960. It is 1,000,000. Huawei's newly disclosed Peerium architecture aims to make systems of up to a million processors behave like a single giant computer, using nested parallel processing, a unified memory address space, and peer-to-peer connections between processors.
The facts here need a clear boundary. A million-processor system is not already running. What Huawei has officially confirmed as currently being deployed is the Atlas 950 SuperCluster, at a scale of 256,000 cards. One million is the scale Peerium is aiming for, and the Atlas 960 series systems are still in testing.
Total AI performance is not "chip speed times chip count"
A more accurate way to think about large AI systems looks like this:
Effective AI performance ≈ chip performance × chip count × real utilization rate
Chip → Rack → Cluster → Data Center
Multiply the number of chips by ten and performance does not multiply by ten if the chips spend more time waiting to exchange data with each other. During training, huge numbers of accelerators must exchange and synchronize parameters and intermediate results at every single step. If one falls behind, the rest wait for it. This is the straggler problem, where the slowest worker sets the pace for the entire iteration.
Why Huawei's 20% figure matters
At the event, Huawei said that as clusters scale up under conventional computing architectures, resource utilization tends to fall, and that the real model-compute utilization of a traditional 100,000-card cluster can be as low as roughly 20%. This figure comes from Huawei itself, so it should not be treated as an independently verified industry average. Still, it is a useful signal for what the core challenge of massive-scale clusters actually is.
20% — The model-compute utilization rate Huawei cited as an example for a traditional 100,000-card cluster. The claim is that as scale grows, communication delays can eat into actual computation.
256,000 — The number of cards in the Atlas 950 SuperCluster that Huawei says is currently being deployed. Unlike the million-chip figure, this scale has been officially confirmed as real.
1,000,000 — The processor-scale target for Peerium. Real-world competitiveness will depend not on this number itself but on how much utilization and stability can be maintained at that scale.
What gets harder at a million chips
| Bottleneck | Why it grows | What the system must solve |
|---|---|---|
| Networking | More accelerators mean simultaneous traffic and congestion explode. | High bandwidth, low latency, congestion control, efficient collective communication |
| Memory | Massive models do not fit in a single accelerator's memory. | Memory pooling, KV cache management, minimizing data movement |
| Synchronization | If some nodes lag, the entire training iteration waits. | Workload splitting, scheduling, straggler mitigation |
| Reliability | With more components, some failures become routine, not exceptions. | Fault isolation, checkpointing, automatic restart, failover paths |
| Power & Cooling | Networking and memory consume power too, not just compute. | Power density, liquid cooling, optical interconnects, data center design |
| Software | More hardware only helps if programs can use it efficiently. | Compilers, libraries, runtimes, distributed training and inference frameworks |
Nvidia's moat sits outside the GPU itself
Seen this way, Huawei's Peerium is both a technology that threatens Nvidia and a mirror that shows why Nvidia is strong. Nvidia's GB300 NVL72 links 72 Blackwell Ultra GPUs over NVLink so they act as one giant accelerator, delivering a total of 130TB/s of GPU-to-GPU communication bandwidth inside the NVLink domain. At larger scale, Spectrum-X Ethernet and InfiniBand connect thousands to tens of thousands of GPUs beyond the rack.
Nvidia does not stop there. CUDA ties together the developer ecosystem, NCCL and other communication libraries handle distributed computation, and Dynamo coordinates KV cache, routing, and autoscaling for distributed inference. Nvidia's product, in the end, looks less like a "GPU" and more like an entire system that keeps GPUs working at high utilization without interruption.
Huawei is trying to solve the same problem with UnifiedBus at the center of its strategy, connecting CPUs, NPUs, memory, SSDs, NICs, and switches under a single protocol, with plans to bring near-packaged optics to future Atlas 960 systems. The two companies are working from different technology stacks, but heading toward the same conclusion. The core of the AI race is not the chip that generates FLOPS, but the system that keeps those FLOPS from going to waste.
Insight Times Editorial Desk
